SetResetTypeFlipFlop

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SetResetTypeFlipFlop

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Library

Signal\Logical\Real

Use

Domains: Discrete, Continuous. Size: 1-D. Allowed in: Block Diagrams.

Implementations

This model has a continuous-time and a discrete-time implementation.

Continuous
Discrete

Description

The initial output of this model is equal to the parameter initial. Otherwise the output signal is according the truth table below:

 

set

reset

output

 

false

false

previous output

 

true

false

true

set condition

false

true

false

reset condition

true

true

true

set condition

 

with

 

false

true

inputs

<= 0.5

> 0.5

output

0

1

 

The truth table shows an S-dominated latch, meaning that if both set and reset are true, the set input dominates.

Interface

Port name

Data type

Description

Range

Inputs



 

set

boolean

set input

<= 0.5 / > 0.5

reset

boolean

reset input

<= 0.5 / > 0.5

Outputs



 

output

boolean

output

0 or 1

Parameters



 

initial

boolean

initial output

<= 0.5 / > 0.5

 

Restrictions

This block operates with real inputs. Boolean inputs can also be used but will lead to a warning during processing.