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Navigation: Library > Signal > Logical > Real > SetResetTypeFlipFlop |
  
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Signal\Logical\Real
Domains: Discrete, Continuous. Size: 1-D. Allowed in: Block Diagrams.
This model has a continuous-time and a discrete-time implementation.
| • | Continuous |
| • | Discrete |
The initial output of this model is equal to the parameter initial. Otherwise the output signal is according the truth table below:
set |
reset |
output |
|
false |
false |
previous output |
|
true |
false |
true |
set condition |
false |
true |
false |
reset condition |
true |
true |
true |
set condition |
with
|
false |
true |
inputs |
<= 0.5 |
> 0.5 |
output |
0 |
1 |
The truth table shows an S-dominated latch, meaning that if both set and reset are true, the set input dominates.
Port name |
Data type |
Description |
Range |
Inputs |
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set |
boolean |
set input |
<= 0.5 / > 0.5 |
reset |
boolean |
reset input |
<= 0.5 / > 0.5 |
Outputs |
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output |
boolean |
output |
0 or 1 |
Parameters |
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initial |
boolean |
initial output |
<= 0.5 / > 0.5 |
This block operates with real inputs. Boolean inputs can also be used but will lead to a warning during processing.