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Library
Modeling Tutorial

ResetSetFlipFlop

Navigation: Library > Signal > Logical > Boolean >

ResetSetFlipFlop

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Library

Signal\Logical\Boolean

Use

Domains: Discrete, Continuous. Size: 1-D. Allowed in: Block Diagrams.

Implementations

This model has a continuous-time and a discrete-time implementation.

•	Continuous

•

Discrete

Description

The initial output of this model is equal to the parameter initial. Otherwise the output signal is according the truth table below:

set	reset	output
false	false	previous output
true	false	true	set condition
false	true	false	reset condition
true	true	false	reset condition

The truth table shows an R-dominated latch, meaning that if both set and reset are true, the reset input dominates.

Interface

Port name	Data type	Description	Range
Inputs
set	boolean	set input	false/true
reset	boolean	reset input	false/true
Outputs
output	boolean	output	false/true
Parameters
initial	boolean	initial output	false/true

Restrictions

This block operates with boolean inputs. Real of integer inputs can also be used but will lead to a warning during processing. Be careful with using real or integer inputs: A value of 0.0 is converted to false, any other value is converted to true.