Signal\Logical\Real
Domains: Discrete, Continuous. Size: 1-D. Allowed in: Block Diagrams.
The output signal of this model is according the truth table below:
|
false |
true |
||||
false |
false |
|
||||
true |
true |
|
with
|
false |
true |
inputs |
<= 0.5 |
> 0.5 |
output |
0.0 |
1.0 |
Inputs |
Description |
input1 input2 |
|
Outputs |
|
output |
|