Or

Navigation:  Library > Signal > Logical > Real >

Or

Previous pageReturn to chapter overviewNext page

Library

Signal\Logical\Real

Use

Domains: Discrete, Continuous. Size: 1-D. Allowed in: Block Diagrams.

Implementations

This has 8 implementations varying from a 2-input AND to a 9-input AND.

inputs_2
inputs_3
inputs_4
inputs_5
inputs_6
inputs_7
inputs_8
inputs_9

Description

The output signal of this submodel for the two-input OR is according the truth table below:

 

input1

input2

output

false

false

false

false

true

true

true

false

true

true

true

true

 

with

 

false

true

inputs

<= 0.5

> 0.5

output

0

1

 

The output signal for the other OR implementations follows a similar pattern. The output signal is only 0 when all input signals are equal to 0.

Interface

Port name

Data type

Description

Range

Inputs




input1

real

First OR input

<= 0.5 / > 0.5

input2

real

Second OR input

<= 0.5 / > 0.5

Outputs



 

output

real

Result of the OR operation

1 or 0

 

Restrictions

This block operates with real inputs. Boolean inputs can also be used but will lead to a warning during processing.