CompareGE

Navigation:  Library > Signal > Logical > Real >

CompareGE

Previous pageReturn to chapter overviewNext page

Library

Signal\Logical\Real

Use

Domains: Discrete, Continuous. Size: 1-D. Allowed in: Block Diagrams.

Description

This model compares two input real signals and outputs the result as 0 or 1 according to the following table:

 

inputs

output

input1 >= input 2

1

input1 < input 2

0

 

Interface

Port name

Data type

Description

Range

Inputs



 

input1

real

First input

real

input2

real

Second input

real

Outputs



 

output

real

Result of the input1 >= input2

1 or 0