CMOS_CD4020

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CMOS_CD4020

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Library

Signal\Logical\Real

Use

Domains: Discrete, Continuous. Size: 1-D. Allowed in: Block Diagrams.

Description

Binary counter modeled after the CMOS 4020 chip. The 4020 is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the 1-to-0 transition of CP. A HIGH on MR clears all counter stages and forces all outputs to 0, independent of the state of CP.

Interface

Port name

Data type

Description

Range

Inputs




CP

real

clock input (HIGH-to-LOW, edge-triggered)

<= 0.5 / > 0.5

MR

real

master reset input (active HIGH)

<= 0.5 / > 0.5

Outputs




Q0 … Q13

real

parallel outputs

1 or 0

 

Restrictions

This block operates with real inputs. Boolean inputs can also be used but will lead to a warning during processing.