Signal\Logical\Boolean
Domains: Discrete, Continuous. Size: 1-D. Allowed in: Block Diagrams.
This submodel has 8 implementations varying from a 2-input AND to a 9-input AND.
• | inputs_2 |
• | inputs_3 |
• | inputs_4 |
• | inputs_5 |
• | inputs_6 |
• | inputs_7 |
• | inputs_8 |
• | inputs_9 |
The output signal of this model is according the truth table below:
input1 |
input2 |
output |
false |
false |
false |
false |
true |
false |
true |
false |
false |
true |
true |
true |
The output signal for the other AND implementations follows a similar pattern. The output signal is only true when all input signals are equal to true.
Port name |
Data type |
Description |
Range |
Inputs |
|||
input1 |
boolean |
First AND input |
false/true |
input2 |
boolean |
Second AND input |
false/true |
Outputs |
|||
output |
boolean |
Result of the AND operation |
false/true |
This block operates with boolean inputs. Real of integer inputs can also be used but will lead to a warning during processing. Be careful with using real or integer inputs: A value of 0.0 is converted to false, any other value is converted to true.