Clock

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Clock

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Library

Signal\Logical\Real

Use

Domains: Discrete, Continuous. Size: 1-D. Kind: Block Diagrams.

Implementations

This model has a continuous-time and a discrete-time implementation.

Continuous
Discrete

Description

This models generates a logical continuous clock signal, i.e. a signal that changes from true (1) to false (0) and back, each period T with T = (1/frequency)

 

Clock-Discrete

If the discrete implementation is chosen, the frequency must be smaller than half of the  the sample frequency, otherwise not a good clock signal will result. To have the top part of the clock signal equally long to the down part, choose the frequency equal to the sample frequency divided by 2^n, with n an integer equal or larger than one.

Interface

Port name

Data type

Description

Range

Parameters



 

initial

real

initial output

<= 0.5 / > 0.5

frequency

real

clock frequency {Hz}

> 0.0  Hz

Outputs



 

output

real

Clock output

1 or 0

 

Restrictions

Make sure that the simulation uses step sizes which are small enough to calculate the clock signal going up and going down: step size << clock period.