da-delay

Navigation:  Library > Signal > Discrete >

da-delay

Previous pageReturn to chapter overviewNext page

Library

Signal\Discrete

Use

Domains: Discrete, Continuous. Size: 1-D. Allowed in: Block Diagrams.

Description

This model incorporates the basic functions of a digital to analog convertor: zero order hold, output window (i.e. restriction of the output between a minimum and maximum value) and quantization. The quantisation is specified in bits. For example 8 bits quantisation means the output has 2^8 - 1 = 255 possible values between the given minimum and maximum.

 

The standard models of the discrete library assume that there is no time needed to perform the calculations the a discrete loop. In general these calculations do take time. To take this into account, the output of this model is delayed in time. This time delay can be set by the user and should correspond to the time needed to perform all calculations of the discrete loop in a real system.

Interface

Inputs

Description

input

 

Outputs

 

output

 

Parameters

 

minimum

maximum

bits

t_calc

Minimum output value.

Maximum output value

Quantisation levels (bits).

Time needed to perform all calculations of the discrete loop.

Limitations

The input of this model is a discrete signal. The output of this model is a continuous signal. 20-sim will automatically detect the existence of discrete models. Each chain of discrete models will be assigned a specific sampletime. You can set this sample time to any desired value in the Simulator (choose Properties, Simulation and Discrete System).