Signal\Logical\Boolean
Domains: Discrete, Continuous. Size: 1-D. Allowed in: Block Diagrams.
Binary counter modeled after the CMOS 4020 chip. The 4020 is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the true-to-false transition of CP. A HIGH on MR clears all counter stages and forces all outputs to false, independent of the state of CP.
Port name |
Data type |
Description |
Range |
Inputs |
|||
CP |
boolean |
clock input (HIGH-to-LOW, edge-triggered) |
false/true |
MR |
boolean |
master reset input (active HIGH) |
false/true |
Outputs |
|||
Q0 … Q13 |
boolean |
counter outputs |
false/true |
This block operates with boolean inputs. Real of integer inputs can also be used but will lead to a warning during processing. Be careful with using real or integer inputs: A value of 0.0 is converted to false, any other value is converted to true.