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clock-discrete

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clock-discrete

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Library

Signal\Discrete

Use

Domains: Discrete. Size: 1-D. Allowed in: Block Diagrams.

Description

This models generates a logical discrete clock signal, i.e. a signal that changes from true (1) to false (0) and vice-versa, each sample time.

Clock-Discrete

Interface

Outputs

Description

output

 

Parameters

 

initial

Initial value of the output.

Limitations

The output of this model is a discrete signal. 20-sim will automatically detect the existence of discrete models. Each chain of discrete models will be assigned a specific sampletime. You can set this sample time to any desired value in the Simulator (choose Properties, Simulation and Discrete System).